1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices and particularly to those having a metal oxide nitride oxide silicon (MONOS) configuration.
2. Description of the Background Art
Conventional non-volatile semiconductor memory devices, flash electrically-erasable programmable read-only memories (EEPROMs) capable of electrically writing information to be stored and electrically erasing information stored therein in particular, perform an erase operation for one memory cell region (or block) of a range at a time and a verify operation for one memory cell at a time.
Such a conventional non-volatile semiconductor memory device has been improved, as proposed as follows:
Japanese Patent Laying-Open No. 6-275087 proposes a technique allowing memory cell transistors having xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d written therein, respectively, before over-erasure to have their respective threshold values with a reduced variation therebetween after over-erasure.
Furthermore, Japanese Patent Laying-Open No. 7-272491 proposes that a plurality of memory cells are erased to have an overerased condition and only while a cell/cells leaks/leak a current due to the overerased condition the cell/cells is/are subjected to a write to allow all memory cells to have their threshold values matched to have a prescribed value when they have an erased condition.
As has been described above, conventional non-volatile semiconductor memory devices, flash EEPROMs in particular, perform an erase operation for one memory cell region (or block) of a range at a time and perform a verify operation for one memory cell at a time. As such, the verify operation is disadvantageously more time consuming than the erase operation.
The above disadvantage of conventional non-volatile semiconductor memory devices is resolved by a technique such as disclosed in Japanese Patent Laying-Open No. 6-275087. The technique disclosed in this publication, however, would not permit a simultaneous write operation following overerasure to sufficiently correct a variation in threshold value between memory cell transistors.
Japanese Patent Laying-Open No. 7-272491, proposing that only while a cell/cells overerased leaks/leak a current the cell/cells is/are subjected to a write to allow all memory cells to have their threshold values matched to have a prescribed value when they have an erased condition, does not have any relationship with the issue of the reduction of the verify time.
The present invention contemplates a non-volatile semiconductor memory device that corrects a variation in threshold value between memory cell transistors in a simultaneous write operation following overerasure and also provides a verify operation in a reduced period of time.
In accordance with the present invention a non-volatile semiconductor memory device includes: first, second and third bit lines arranged to extend in a direction of a column; a plurality of memory cells configuring first and second memory cell columns adjacent to each other, each memory cell being configured of a transistor having an electric charge trapping film; and a plurality of word lines provided to correspond respectively to rows of the plurality of memory cells. The first memory cell column is connected between the first bit line and the second bit line and the second memory cell column is connected between the second bit line and the third bit line. The non-volatile semiconductor memory device further includes: an erase control portion controlling an erase operation effected for the plurality of memory cells; and a weak write control portion controlling a weak write operation effected for the plurality of memory cells, and the erase control portion subjects all of the plurality of memory cells simultaneously to an erase operation allowing a memory cell to transition to an overerased condition and the weak write control portion subjects all of the plurality of memory cells simultaneously to a weak write operation using a channel hot electron.
Thus in accordance with the present invention a weak write using a channel hot electron can be used to correct a variation in threshold value between memory cell transistors in a simultaneous write operation following overerasure and also allow a verify operation to be performed in a reduced period of time.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.